Multicore Simulation and Optimized Code Generation Using Infineon AURIX
Infineon AURIX TC4x microcontrollers contain six homogenous TriCore® CPUs (TriCore 0 to TriCore 5) and a heterogeneous parallel processing unit (PPU). You can run different models on the available cores or you can partition complex models to run concurrently on these multiple cores to achieve design modularity. The Interprocess Data Channel block handles communication between the multiple cores. After simulating the multicore model, you can deploy the generated code on an Infineon AURIX TC4x hardware board using the SoC Builder tool and monitor the signals from the hardware using the One Eye tool from Infineon.
The PPU performs computations faster than the TriCores. The PPU core accelerates the performance of the model by using the code replacement libraries to replace parts of generated code with hardware-specific code. The TriCore 0 core is the principal core and it can communicate with all the remaining auxiliary cores (TriCore 1 to TriCore 5 and PPU).
After you create an SoC model by using the multiple cores of Infineon AURIX microcontroller, use the SoC Builder tool to generate executables, code, and program the hardware board. See Getting Started with Multicore Modeling and Targeting for Infineon AURIX TC4x Microcontrollers example to understand how to validate, build, and run a multicore model to generate executables, code, and program the Infineon AURIX TC4x hardware board.
Blocks
Tools
SoC Builder | Build, load, and execute multicore application models on Infineon AURIX TC4x hardware boards (Since R2024b) |
Hardware Mapping | Map tasks and peripherals in a model to hardware board configurations (Since R2022b) |
Topics
- Parallel Processing Unit for Optimized Code Generation
Use PPU to implement models with large data processing requirements or fast execution time requirements.
- PIL Simulation Using nSIM Simulator
Run PIL simulations and test PPU based application models using nSIM simulator.
- Top-Level Models Using TriCores of Infineon AURIX
Simulate, and generate code for top-level models with referenced models using TriCores of Infineon AURIX TC4x microcontrollers.
- Top-Level Models Using TriCores and PPU of Infineon AURIX
Simulate and generate hardware-specific code for top-level models with referenced models using TriCore and PPU cores of Infineon AURIX.
- Single-Core and Flat Models Using TriCore and PPU of Infineon AURIX
Simulate and generate code for single-core and flat models using multiple cores of Infineon AURIX.
- Generate Code and Deploy Using SoC Builder
Generate code and run it on the target hardware board using the SoC Builder tool.
- Generate Software Executables for Multicore Models
Generate ELF file for all participating homogenous cores of Infineon AURIX.
- Task Duration
Set the execution time or duration of a task in Task Manager block.
- What is Task Execution?
Learn the definition of task execution and task life-cycle in a processor.
- Task Execution Playback Using Recorded Data
Replay task execution timing using recorded task timing data from previous simulations or processors.