SoC-Based Multicore Modeling for Infineon AURIX Microcontrollers
System-on-chip (SoC) architecture is a model-based design approach for the multicore systems. In this workflow, you can implement different Simulink® models as model references which can run on individual processing units. A top-level system model in Simulink can represent an entire embedded system. This representation can include application models running on different processing units, their scheduling behavior, plant model, and their interfaces with the system model. This hierarchical modeling approach reflects the SoC architecture and supports integrated simulation, code generation, and deployment. You can use this approach to partition complex algorithms between processing units to analyze the implementation trade-offs.
The SoC Builder tool guides you through the development of multicore SoC application models for Infineon AURIX hardware. This tool also helps you validate your Simulink model, configure the peripherals and interrupts, manage code generation, and build and deploy the application to the hardware board. Develop
Based on your system architecture and design strategy, you can use this tool to develop either a single integrated application across all TriCore® processing units or separate applications for each participating core.
Single executable for all homogenous cores option in the SoC Builder generates a single executable and linkable format (ELF) file for all the participating TriCore processing units of an integrated application designed for tightly coupled multicore systems.
Single executable for each core option in the SoC Builder generates separate ELF files for each participating core of the application models designed for independent core execution.
For more information on generating single and separate executables, see Generate Software Executables for Multicore Models.
Anatomy of SoC Model
An SoC-based multicore model consists of a top-level model that includes at least two Model blocks referencing to unique models and two Task Manager blocks. In simulation, each Task Manager and Model block automatically acts as an independent processor.
In the multicore workflow, you can simulate inter-core communication, interrupt handling, and task partitioning among the participating processing units using the Interprocess Data Read, Interprocess Data Write, Interprocess Data Channel, and Task Manager blocks.
The figure represents an SoC-based multicore model with N Model blocks referencing to unique models. The referenced models must have Interprocess Data Read and Interprocess Data Write blocks to support communication among them via an Interprocess Data Channel block. The Task Manager blocks handle simulation and execution of the software tasks. These tasks can be rates for time-driven tasks or function-call subsystems for the event-driven tasks contained inside a single Model block. Time-driven tasks execute at a periodic rate equal to an integer multiple of the Simulink model fundamental sample time. Event-driven tasks start executing when triggered by an external event such as hardware-generated interrupts. For more information, see Time-Based Scheduling and Event-Based Scheduling.
