I am using HDL coder to generate RTL from simulink.
While in my simulink model, the port is not a single signal but a multiple signal, assume the port name is sig, and it contains 3 signals which shares the same signal path. After RTL generation, HDL coder automatically expand the sig into 3 signals, which are sig_0, sig_1, and sig_2.
My questions is how can I assign the expanded name? I donot like the sig_0, sig_1 and sig_2. In my design, I would like to assign it as sig_x, sig_y, and sig_z.
Thanks a lot!