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HDLCoder timing closure errors on hps2fpga brigde when scaling up a model.

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Dominique Görner
Dominique Görner 2021 年 7 月 9 日
回答済み: Kiran Kintali 2021 年 7 月 12 日
Im trying to scale up a motor control algorithm from 1 controller to 4 instances on HDLCoder in 2018b. The Plattform is a Cyclone V SoC.(Smaller design used a Terasic DE0 Nano SoC Dev Board. Bigger version now uses a MitySom 5CSx. Both where setuped like described in the article "Define Custom Board and Reference Design for Intel SoC Workflow"). The Scaleup caused many timing closure problems. Most of which I could fix by manually inserting pipeline registers. But towards the end of this process, I encountered this timing error.:
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Summary of Paths ;
+--------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
; -1.977 ; system_soc_hps_0:hps_0|system_soc_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2514 ; system_soc_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:gt_current_controller_0_s_axi_wr_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[7] ; hps_0|fpga_interfaces|clocks_resets|h2f_user0_clk ; hps_0|fpga_interfaces|clocks_resets|h2f_user0_clk ; 10.000 ; -0.495 ; 11.412 ;
; -1.959 ; system_soc_hps_0:hps_0|system_soc_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2440 ; system_soc_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:gt_current_controller_0_s_axi_rd_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6] ; hps_0|fpga_interfaces|clocks_resets|h2f_user0_clk ; hps_0|fpga_interfaces|clocks_resets|h2f_user0_clk ; 10.000 ; -0.472 ; 11.417 ;
; -1.948 ; system_soc_hps_0:hps_0|system_soc_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2440 ; system_soc_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:gt_current_controller_0_s_axi_rd_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6] ; hps_0|fpga_interfaces|clocks_resets|h2f_user0_clk ; hps_0|fpga_interfaces|clocks_resets|h2f_user0_clk ; 10.000 ; -0.472 ; 11.406 ;
+--------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+------------+------------+
The FPGAs clock is set to 50 Mhz and I never had any problems with the HPS/FPGA Bridge in the smaller version before.
Since this is outside the scope controlled by my simulink model, I have a hard time seeing how I can provide the required timing closure.
At this point any help is appreciated.
(Im guessing any modification would have to be done during the "Create Project" step of the IP Generation Workflow)

採用された回答

Kiran Kintali
Kiran Kintali 2021 年 7 月 12 日
You can reach out to support@mathworks.com to get additional help on the topic.

その他の回答 (1 件)

Kiran Kintali
Kiran Kintali 2021 年 7 月 12 日
>> Im trying to scale up a motor control algorithm from 1 controller to 4 instances on HDLCoder
This should be possible. Can you share your model?
If you replicated the controller to four parallel controllers, you can try to share them by marking them atomic and setting the SharingFactor. This will add some latency and routing logic but should give you better area.
  1 件のコメント
Dominique Görner
Dominique Görner 2021 年 7 月 12 日
Good to know, but this wont at all change my timing problem in the hps to fpga interconnect.
The other timing errors were mostly due to simulink not properly pipelining gain blocks, with their implementation set to csd.
Im afraid I cannot publicly share my Model. Is there a way to do so privately?

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