How to generate Verilog code from Deep Learning Network in MATLAB?

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Saurabh Kumar Yadav
Saurabh Kumar Yadav 2021 年 6 月 15 日
コメント済み: Kiran Kintali 2021 年 6 月 15 日
I have trained a Deep Learning Network in MATLAb, now I have to genearte a Verilog code for the same. I went through Deep Learning HDL Toolbox, there I found the methods to deploy the network on FPGA but did not get any method to generate a Verilog code. Please help.

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Kiran Kintali
Kiran Kintali 2021 年 6 月 15 日
Deep Learning Processor Customization and IP Generation
Configure, build, and generate custom bitstreams and processor IP cores, estimate and benchmark custom deep learning processor performance
Deep Learning HDL Toolbox™ provides functions to configure, build, and generate custom bitstreams and a custom processor IP. Obtain performance and resource utilization of a pretrained series network on the custom processor. Optimize the custom processor by using the estimation results.
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Kiran Kintali
Kiran Kintali 2021 年 6 月 15 日
please reach out to support@mathworks.com and someone from the MathWorks team can walk you through the steps and show you how to use the feature.

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