QPSK Modulation Verilog Code generation error?

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ali shan
ali shan 2021 年 6 月 4 日
回答済み: Bharath Venkataraman 2021 年 6 月 7 日
Hello
hope you are doing well.
i am using QPSK modulation IP and want to create Verilog code using that but it show me some error like mention in picture

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Bharath Venkataraman
Bharath Venkataraman 2021 年 6 月 7 日
It appears that you need to covert the design to use fixed-point as well as set appropriate sample rates for your sources. Please take a look at this example to see how you can change your design.

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