The fixed-point attributes of the stages of a cascade cannot be changed in FDATOOL. They must be set before cascading

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zhuo yang
zhuo yang 2021 年 3 月 30 日
回答済み: Kiran Kintali 2021 年 3 月 30 日
I want to set an interpolated digital filter to output to Verilog HDL. I can't set the fixed-point input / output bit width parameter. How can I solve this problem：
The fixed-point attributes of the stages of a cascade cannot be changed in FDATOOL. They must be set before cascading

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Kiran Kintali
Kiran Kintali 2021 年 3 月 30 日
Consider creating a simulink model and generating Verilog HDL from the generated model after further customizations.

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