Implementation of median filter on FPGA
6 ビュー (過去 30 日間)
古いコメントを表示
VANISHREE M
2020 年 1 月 14 日
回答済み: Bharath Venkataraman
2020 年 1 月 20 日
Hi everyone, I want to design the median filter on FPGA. I got the output for median filter in matlab and also in matlab simulink. but i want to know how to convert the matlab code or matlab simulink model to hdl code(verilog). Because i am new to matlab please help me to do that. In hdl workflow advisor, they ask test bench how to write the test bench for image processing????
0 件のコメント
採用された回答
その他の回答 (1 件)
Bharath Venkataraman
2020 年 1 月 20 日
Are you able to generate VHDL (which is the default), or is there an error during HDL code genration?
The last section (Generate HDL Code and Verify Its Behavior) describes how to generate HDL code. You can add a property-value pair to generate Verilog.
makehdl('NoiseRemovalAndImageSharpeningHDL/Pixel-Stream HDL Model','targetLanguage','Verilog')
0 件のコメント
参考
製品
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!