How to determine where HDL coder's clock-rate pipelining runs into an algebraic loop?

When I try to generate HDL for my DUT subsystem, hdl coder fails with the following error:

"Delay balancing unsuccessful because Clock-rate pipelining was applied in a feedback loop and introduced a sample step delay. Consider increasing the Oversampling factor."

Ashow and some of the other algebraic loop search methods show nothing. highlightClockRatePipelining.m does not seem to higlight the problem spot either. Is there an automated way to show the point where the failure occurs?

Answer 1

[Kiran Kintali]

Please reach out to [e-mail] with reproduction steps. It looks like the highlight script that points to the problem broken for your design and may need to be enhanced.