Merging separate vivado project into RF SOM reference design and using external target interface

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Brian Banks
Brian Banks 2019 年 6 月 11 日
回答済み: Kiran Kintali 2021 年 6 月 30 日
Hi All,
I am using Simulink and the coders (HDL and embedded) to develop a system on an analog devices’ RF SOM SDR(ADRV9361-Z7035) and using a BOB carrier board(ARDV1-CRR-BOB).
I used the HDL workflow advisor to generate a hdl bitstream and software interface model. There is a separate vivado project that contains digital logic that I would like to incorporate into the bitstream that is created by the workflow advisor.
My question is how would I go about combining them into one bitstream that would be loaded on the RF SOM board? Would it be a matter of opening up the hdl workflow generated vivado project and copy the blocks from the other vivado project make the connections and generate a bitstream?
The project contains 4 data and 4 clock signals that need to be routed to the separate vivado IP. Then there are signals from the separate project that are routed back to using the external port interface(section 1.3 of the hdl workflow advisor) to output data and handshaking signals to an external board.
Any details on how this can be achieved and more information on how the external target interface can be implemented would be greatly appreciated.
Thanks in advance,
Brian B.

回答 (1 件)

Kiran Kintali
Kiran Kintali 2021 年 6 月 30 日
If this question is about merging multiple IP blocks built under different projects into a single bitstream, please contact support@mathworks.com about how to achieve such workflow using HDL Coder.

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