MATLAB 2018a HDL-coder : Failed Program target FPGA device.

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michael brewin
michael brewin 2019 年 1 月 16 日
編集済み: Kiran Kintali 2021 年 6 月 22 日
Hi.
I am Using MATLAB 2018a, HDL coder,
( Now following installing a patch file from Mathsworks (Kiyoko) that fixes step 1.3 in setting the Target device - see July 13 2018 ANSWERS post from Dean Oswald )
for the "hdlcoder_led_blinking.slx" example.
The code now builds a FPGA bitsteam file, but the last step (programming) now fails ; - HDL coder section 4.4 "Program The Target device".
Failed Program target FPGA device.
ask "Program Target Device" unsuccessful. See log for details.
Generated logfile: C:\ALL\SOAR\MATLAB_DEV\hdl_prj2018a\hdlsrc\hdlcoder_led_blinking\workflow_task_ProgramTargetDevice.log
Downloading target FPGA device configuration over Ethernet to SD card ...
Error executing command "mw_setboot '/tmp/hdlcoder_rd/hdlcoder_system.bit' 'devicetree_axilite.dtb' '/tmp/hdlcoder_rd' 'Default system'". Details:
STDERR:
STDOUT: # Copied /tmp/hdlcoder_rd to /mnt/hdlcoder_rd
# Copying Bitstream hdlcoder_system.bit to /mnt/hdlcoder_rd
# Set Bitstream to hdlcoder_rd/hdlcoder_system.bit
ERROR: Devicetree /mnt/devicetree_axilite.dtb not found
ERROR: Failed to set the target devicetree
What is reported is true, the Devicetree_axilite.dtb does not exist. I can see the /mnt directory from a terminal.
/mnt/devicetree_axilite.dtb
Networking & serial comms to the Zedboard containing the Zynq device, seems to be fine, I can ping each way.
{The Zedboard is on a private ethernet link, the host machine is set to 192.168.30.3 and the Zedboard 192.168.30.2.}
The comms definately starts, becuase the Programming step fails earlier unless the COM port terminal is shut down.
( I thought the "download" method would be network-only, if you could explain the involvement of sertial, it would help...)
{ Note : I am sure this programming step has worked previously, perhaps if I targetted a generic-ASIC/FPGA workflow,
becuase my Zedboard is blinking it's red LED , This must mean that the hdl code did download and I guess program and store the HDL,
becuase the red LED now blinks from boot. ( it didn't, before I started work on this example )
So,,, is the programming 1-shot and the Zedboard SD card image require regenerating from new ?
When I got it to work, I may have not set the hdlcoder to IP core generation workflow,,,,
I might have to put in support case on this :-
( I have been generating hdl using the generic ASCI/FPGA workflow to check my code for some time without issue)
Regards,
Dr Michael Brewin. - Mike
This is the report of Z= zynq() in MATLAB that I ran after the failure.
>> z= zynq
z =
LinuxShell with properties:
IPAddress: '192.168.30.2'
Username: 'root'
Port: 22
  6 件のコメント
Noam Levine
Noam Levine 2019 年 1 月 22 日
Mike - Glad the problem is resolved. The folks I talked to here felt that the error message pointed to an SD card that didn't get programmed correctly (missing the device tree for some reason).
-noam

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回答 (1 件)

Kiran Kintali
Kiran Kintali 2021 年 6 月 22 日
編集済み: Kiran Kintali 2021 年 6 月 22 日
(per Kiyoko notes)
There are some old ISE reference designs shipped in Zynq Hardware Support Package. These cause confusion. HDL Coder is deprecating Xilinx ISE reference designs for shipping Zynq boards. The programming method Download no longer works in these reference designs.
These ISE reference designs are not needed, as one can use Vivado on all the Zynq devices. We cannot completely remove ISE support, for usage with Spartan6 there is still need to support Xilinx ISE.

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