Internal error in Simulink Design Verifier back end

I have an unexpected internal error in Simulink Design Verifier, with Matlab r2018a, as below: "An unexpected internal error occured in Simulink Design Verifier.If you can reproduce this problem, please report it to Mathworks by copying this log contents and including the .dvo file contained in the directory: <path>". What can I do?

Answer 1

[madhan ravi]

As it states send the error log to the Matheorks support team by clicking Contact Us button on this page . They will guide you further.