How to resolve the exceed of maximum supported wordlength of 128 bits in hdlcoder?
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Dear All, I'm trying to implement the below equation in hdlcoder, But I've encountered "The computed word length of the result is 186 bits. This exceeds the maximum supported wordlength of 128 bits."
How can I resolve this problem?
out = (((389.12*d*d*d*d*d - 113.19*d*d*d*d + 131.1*d*d*d - 60.671*d*d + 3.7314*d + 50.1321)*(Y*Y*Y*Y*Y) + ...
(-112.11*d*d*d*d*d + 10.5*d*d*d*d - 43.21*d*d*d + 19.54*d*d - 4.048*d - 1.695)*(Y*Y*Y*Y) + ...
...
...
(1.16*d*d*d*d*d - 1.11*d*d*d*d + 4.38*d*d*d - 1.28*d*d - 5.097*d + 3.764)*(Y*Y*Y) + ...
(-90.05*d*d*d*d*d + 201.5*d*d*d*d - 3.94*d*d*d + 1386.7389*d*d - 714.54729*d + 0.36295))*1024);
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採用された回答
Kiran Kintali
2020 年 8 月 23 日
HDL Coder supports various data types for synthesis. If you need high dynamic range in computation you need to use native floating types https://www.mathworks.com/videos/generate-native-floating-point-fpga-implementations-for-field-oriented-control-of-motors.html
If you need to use fixed-point types you need to limit intermediate type growth as the word length limitation for HDL code generation is 128bits.
Another approach to use is to split computation into multiple variables and use vectors of bundled data to carry related computations.
1 件のコメント
Xisheng Yu
2024 年 10 月 15 日
Hi, when I do HDL code generation in Simulink, I get an error warning “The computed word length of the result is 130 bits. This exceeds the maximum supported wordlength of 128 bits.The formula is as follows:a=1-2*q2^2-2*q3^2.How can I solve this problem?Looking forward to your reply
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