How to Implement Configurable Sequence Reordering with N-Way Parallel Outputs Using HDL Coder?
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## Problem Description
Dear community members,
I am seeking guidance on implementing a configurable sequence reordering system with parallel outputs using HDL Coder. Here are the detailed requirements:
### Requirements
1. **Input Sequence**:
Continuous data stream:
$$ x_1, x_2, \dots, x_L, x_{L+1}, \dots, x_{NL} $$
2. **Output Structure**:
- **N parallel outputs** with **L+1 elements per output**.
- Adjacent outputs overlap by **1 element**:
- *Output 1*: $ \{x_1, x_2, \dots, x_L, x_{L+1}\} $
- *Output 2*: $ \{x_{L+1}, x_{L+2}, \dots, x_{2L}, x_{2L+1}\} $
- ...
- *Output N*: $ \{x_{(N-1)L+1}, \dots, x_{NL}\} $
3. **Configurable Parameters**:
- $ L $: Overlap interval (output length = $ L + 1 $).
- $ N $: Number of parallel output channels.
Thank you in advance for your expertise.
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回答 (1 件)
Bharath Venkataraman
2025 年 6 月 2 日
編集済み: Bharath Venkataraman
2025 年 6 月 3 日
The Tapped Delay block can give you the last L values (based on teh delay setting). You can add in additional logic to pick out the values at the times you need.
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