How to generate Generic VHDL from simulink for sysgen model?
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I have used xilinx basic blocks to design a model. I wanted to generate generic VHDL without xilinx specific references. Eventhough i have choosen Behavioural HDL for implementation generated vhdl consist of xilinx specific DFlip-Flop and SRLUTs. Kindly let me know if there is a way? if the option is not being applied then how can we write a matlab sript to set automatically without doing it manually?
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Kiran Kintali
2024 年 8 月 2 日
編集済み: Kiran Kintali
2024 年 8 月 2 日
HDL Coder by default generates generic RTL. The RTL is vendor independent but target optimized. The generated RTL can be taken to any FPGA/SoC or an ASIC.
Can you let us know what you mean by Xilinx specific RTL. There is only one instance when you request use of the Floating Point library for Xilinx you would see any Xilinx specific floating point library primitives.
Please share a sample model for reference.
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Kiran Kintali
2024 年 8 月 2 日
Can you confirm you use HDL Coder? https://www.mathworks.com/products/hdl-coder.html
Try these commands and check the synthesizable generated code
>> sfir_fixed
>> makehdl('sfir_fixed/symmetric_fir')
Keththura
2024 年 8 月 2 日
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