HDL Coder Vivado timing report shows infinite slack

I'm using HDL coder to deploy a controller model in simulink onto Speedgoat FPGA, at the build bitstream stage i get a message saying 'Run build process passed with timing: Timing constraints met.'. But when i open the timing report, in the min delay paths section i see some paths with infinite slack? is this something that would affect the FPGA performance? If so how can i fix this?

Thank you in advance

Answer 1

[Shlok]

Hi Yeung,

Slack is used for measuring the degree of flexibility or buffer time available within a project schedule. It indicates how much a task can be delayed without impacting the overall project timeline. A positive slack indicates that the signal arrived much faster than the required time, whereas a negative slack indicates that the signal path is slower than the required time. Hence, if the slack is infinite, that means the signal is delayed indefinitely.

Seeing "infinite slack" in the minimum delay paths section of your FPGA timing report means that those paths are not constrained or are not used in your design. These paths won't impact the FPGA's performance if they are indeed unused or irrelevant to the critical data paths.

You can also refer to the following MathWorks Documentation link, to know more about “slack”:

https://www.mathworks.com/help/hdlcoder/ug/resolve-timing-failures-in-ip-core-generation-and-generic-asicfpga-workflows.html

Hope this helps.