mapping lookup table to block ram

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xiaodong yu
xiaodong yu 2023 年 11 月 27 日
コメント済み: xiaodong yu 2024 年 9 月 18 日
I use HDL coder, lookup table block. and enable the option to map look up table to RAM. I have add a piple register right at the lookup table output.
when running HDL code generation, I get warning that:
"LUTMapToRAM option is set to ON. this option is used to map lookuptable to a block RAM in hardware. To disable pipeline insertion for mapping lookup tables to RAM, please set the option to "OFF"
what is the meanning of the warning? I have manually added piple register, so I should set the option to OFF? But if I set it to OFF, will the LUT map to Block RAM?
Regards
XD

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Sumukh
Sumukh 2024 年 9 月 17 日
Hi xiaodong,
I am assuming that your model contains a LUT block to process input data and a pipeline register block at the output of the LUT. A similar example model to the model you are referring to is available in the following documentation:
The example model has two subsystems with a lookup table (LUT):
  • LUT_BRAM”: This subsystem is already optimized with a pipeline register block at the output of the LUT. When synthesized, the LUT is efficiently mapped to the block RAM without any pipeline insertions.
  • LUT”: This subsystem has a LUT with no optimizations done to it.
The message about the “LUTMapToRAM” option is a diagnostic message rather than a warning. It appears in the “Diagnostic Viewer” tab when HDL code is generated for the “LUT” subsystem with necessary pipeline insertions to optimize the LUT output. The message states:
  • The “Map lookup tables to RAM” option in the “HDL Code Generation” > “Optimization” > “Pipelining” tab in the “Model Configuration Parameters” dialog box has been enabled.
  • This option provides optimization to the “LUT” subsystem using pipeline insertions by adding a “Delay” block labelled “Pipeline Register” to the output of the LUT.
  • The output delay allows the HDL Coder to efficiently map the LUT to the block RAM.
The option must be checked regardless of presence of the “Delay” block to map the LUT to the block RAM.
The message about the “LUTMapToRAM” option will disappear from the Diagnostic Viewer if the “Delay” block is inserted beforehand at the output of the LUT in the “LUT” subsystem, just like the one inserted in the “LUT_BRAM” subsystem. The “LUT” subsystem is now modelled to map to block RAM efficiently and pipeline insertion is not required anymore.
The modified example model to validate this process has been attached to this answer. You can follow the modelling pattern used either in the documentation or the attached model to verify that the message indeed disappears in your model.
I hope this answers your query.
  1 件のコメント
xiaodong yu
xiaodong yu 2024 年 9 月 18 日
Hi Sumukh
Thanks for your answer. I download the example and compiled different "LUT"s and checked the messages from HDL coder. The message about "LUTMapToRAM" disappears if the module has no manually inserted pipeline register after LUT, which is the case of the "LUT" subsystem.
I also complared the HDL codes of LUT_BRAM, the codes are the same no matter enable or disable the option "map LUT to RAM"
The message of 'LUTMapToRAM' seems to tell user that the pipeline register is alreay placed at LUT output, and FPGA synthesiser can map the generated HDL code to BRAM. Thus, no need to enable the option of LUTMapToRAM here. is this correct?
Regards
XD

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