xiaodong yu

Last seen: 23日前 | 2023 年からアクティブ

Followers: 0 Following: 0

統計

ランク
184,679
of 297,950

評判
0

コントリビューション
7 質問
1 回答

回答採用率
28.57%

獲得投票数
0

バッジを表示

Feeds

質問

Do the additional delays added by adaptive pipeline distroy the alignment between signal paths?
Hi, I want to use adaptive pipeline to optimize the multiply-add module in HDL coder for xilinx FPGA. I enable adaptive piplin...

4ヶ月前 | 1 件の回答 | 0

1

回答

回答済み
HDL Coder reset control
Hi Androw I want to find out all the delay module with "default reset". I use following command, but it is failed. do you have ...

10ヶ月前 | 0

質問

mapping lookup table to block ram
I use HDL coder, lookup table block. and enable the option to map look up table to RAM. I have add a piple register right at th...

1年以上前 | 1 件の回答 | 0

1

回答

質問

HDL simulation logic analyzer is slow
my logic analyzer in HDL simulation is slow. can graphic card help on it or adding more grafic memery?

1年以上前 | 0 件の回答 | 0

0

回答

質問

HDL "complex to Magnitude and angle" module show critical path which can not meet 160MHz clock timing
Hi, experts I try to use the module of "complex to Magnitude and Angle (CMA)" on xilinx FPGA with clock of 160MHz. the critica...

2年弱前 | 1 件の回答 | 0

1

回答

質問

timing control module _tc.v have failed path to other module
my HDL code from HDL codeGen has timing error. Some of the failed path are from module _tc.v to other modules. in the tc.v mod...

2年弱前 | 0 件の回答 | 0

0

回答

質問

wlanhdlreceiver use only 64 sample to do fine symbol timming. is it enough for 40M, 80M and 16MHz wlan signal?
I am learning on the wlanHDLReceiver HDL design. the Design uses 64 data to do fine symbol timing. But in Matlab .m reference de...

2年弱前 | 1 件の回答 | 0

1

回答

質問

evm demoded from wlan ofdm signal with comm.Phasenoise() increased round 3dB from 80MHz to 160MHz signal bandwidth.
Hi, I am using a comm.Phasenoise to check the phase noise effect on EVM for a demoduation of wlan ofdm signal. the simulation...

2年弱前 | 0 件の回答 | 0

0

回答