HDL Coder, Assertion failed: B:\matlab\src\cgir_hdl\dom_pir_core\dutinfo.cpp:101:portIdx < m_inportMap.size()
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I have a HDL Coder Simulink Model in R2021a. The model consists of a generator and a controller. I'm trying to convert the controller model into VHDL and deploy it on Speedgoat, I have discretized the model and converted all data types to fixed-point.
I ran the HDL Coder Workflow in Simulink Real-Time FPGA I/O mode, everything worked fine until I received the error messages below when I was trying to generate RTL code and IP Core.
Failed Assertion failed: B:\matlab\src\cgir_hdl\dom_pir_core\dutinfo.cpp:101:portIdx < m_inportMap.size()
Error using hdlcoder.network/getHDLInputPortNames
Assertion failed:
B:\matlab\src\cgir_hdl\dom_pir_core\dutinfo.cpp:101:portIdx < m_inportMap.size()
Error in hdlturnkey.elab.ModelCodegenIOMultiMap/portReOrderTransform
Error in hdlturnkey.elab.ModelCodegenIOMultiMap/buildModelIOToCodegenIOMap
Error in hdlturnkey.elab.DUTLayer/getDUTCodeGenPIRInfo
Error in hdlturnkey.elab.BoardElaboration/getDUTCodeGenPIRInfo
Error in hdlturnkey.TurnkeyDriver/makehdlturnkey
Error in slhdlcoder.HDLCoder/makehdlturnkey
Error in downstream.DownstreamIntegrationDriver/runIPCoreCodeGen
Error in generateIPCore
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck
Error in ModelAdvisor.Node/runTaskAdvisor
Error in ModelAdvisor.Node.runtohere>runToBreakpoint
Error in ModelAdvisor.Node.runtohere
Does anyone know what could be going on here? How can I fix this? Much appreciated!
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回答 (1 件)
Kiran Kintali
2023 年 5 月 11 日
編集済み: Kiran Kintali
2023 年 5 月 12 日
Can you share the model? This is not an expected error.
Please reach out to MathWorks tech support and they can help you with the workaround.
This might mostly resolved in the latest releases since R2021a.
HDL Coder Bug Reports https://www.mathworks.com/support/bugreports/?&product[]=HD
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