XADC in System Generator/Model Composer for MATLAB

Hi.

I have designed and simulated my entire control logic (using Xilinx blockset of System Generator-Model Composer for MATLAB) and tested in Simulink environment.

Now I need to emulate the ADC register access and controls for the four-channel XADC and set the pin names, etc. How to program/emulate/ design code for XADCs on 7 series FPGA (I use the Nexys A7 board - Artix 7 100t processor) using Xilinx blockset?

I have no experience with programming in Verilog/VHDL. I generate HDL code using System Generator and then generate bitstream and program hardware in Vivado 2020.2.

There are no resources anywhere for XADC emulation / programming using Xilinx blockset. Please help.

I did see some pages where verilog or vhdl files are written and loaded into a black box in Simulink. But I didn't understand it or how it works.

Answer 1

[Kiran Kintali]

Can you share your Simulink model?

Are you trying to utilize HDL Coder workflow advisor IP core generation features?

https://www.mathworks.com/discovery/ip-core-generation.html

https://www.mathworks.com/help/supportpkg/xilinxzynq7000/custom-ip-core-generation.html

https://www.mathworks.com/help/hdlcoder/generate-ip-core-and-bitstream.html

[SUHANYA M S]

I don't use the HDL Coder Kiran. I've installed Vitis 2020.2, which comes with the Model Composer 2020.2 (earlier System Generator) for MATLAB. When MATLAB is launched from Model Composer, the Xilinx Blockset appears in the Simulink Library. I've used blocks from this blockset to design a control algorthim for an application, which I unfortunately cannot share at this point of time.

So far I gave the inputs from Simulink blockset itself using Gateways to the controller. Now I need to incorporate the timing diagrams of the XADC considering how the data will actually be generated by the XADC on the FPGA board.

Vivado 2020.2 has various IP cores and has one for the XADC in 7-Series XIlinx FPGAs.

http://www.physics.umd.edu/hep/drew/programmable/ug480_7Series_XADC.pdf

https://logictronix.com/wp-content/uploads/2020/07/XADC_Debugging_with_ILA_Reference_Guide_Jan28_2019.pdf

A blog has given the steps to include this IP (as a verilog or vhdl file) in Simulink using the Black Box block from Xilinx Blockset.

https://naikvihang.wordpress.com/2011/09/28/matlabise-co-simulation-using-system-generator-for-spartanvirtex-fpgas/

The issue is I've no idea about how to make this work for 4 ADC channels. Most of the resources show how to design using code in the Vivado environment, and not the Simulink environment.

https://ahmedmohamed45am.wixsite.com/fpgagate/single-post/2018/03/15/xilinx-adc-part2-multiple-analog-inputs

I need to access registers in the associated Status and Control registers for this. I don't know how to make this work in Simulink. Will Simulink recognize this IP during compilation? How will this IP be interpreted? I've no clue as there are literally NO resources in this regard anywhere.

[SUHANYA M S]

I noted the link mentioned in your reply. My board is the Nexys A7.