Hello! I am currently working on a project for which my task is to develop a control algorithm for a power converter. This algorithm must be implemented inside an FPGA where the other modules are developped by another person. I decided to use HDL Coder to avoid coding the algorithm, and also insure rapid iterations afterward if corrections are needed (change of controller, architecture,...).
The FPGA is a Xilinx Spartan6, and thus the synthesis tool is included in ISE suite.
My question is:
When I use the workflow advisor, I cannot obtain any result on the timing analysis (Max Frequency) that would help me adding pipelines to my design in order to increase the Frequency. It seems that it considers the module I am generating as a TOP-level, and then tries to bind the I/Os of this module to IOBs. These I/Os are in fact connected to our register base (several 18-bits data). I thus have a message in the synthesis telling me that "more than 100% of the device ressources are used", which is not really the case. Mapping is therefore not possible, and it seems that the workflow advisor needs to perform mapping and P&R to obtain the critical path.
*==> Is it possible to specify that my module is not a TOP and use only the synthesis results as timing inputs to be highlighted in my Simulink Model?*
==> Are there any other options to allow me using this highlighting functionnality in order to place the required pipelines?
I am asking this question because when I give our FPGA expert the generated sources, he's able to perform a synthesis and find the critical path and Minimum Period of the design.
MATLAB/Simulink/HDL-Coder version: 2013b
Thanks by advance for your help. Regards