Code Generation for d flipflop
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Rajini Gajula
2022 年 4 月 22 日
コメント済み: Rajini Gajula
2022 年 5 月 4 日
Hi team,
i have D Flipflop in my simulink model ,when i am trying to generate vhdl code from the model i am getting the error like " Input port 'D' must not have 'Latch input by delaying outside signal' selected for HDL code generation".Please suggest me how i can proceed further by resolving this error.
Best Regards,
Rajini
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Bharath Venkataraman
2022 年 4 月 25 日
Do you really need to model the D Flip Flop (especially the clock)? If not, I suggest using the Delay block (with enable if you need it). The generated HDL will have a clock port you can drive in the hardware.
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