Numerator of FIR filter using "firpm" command is not working properly for ZYNQ 706

I am using FIR filter as bandpass fiter in my model whenever i pass the parameters in normal simulink model using "firpm" command in simulink it properly filters the desired signal but when i use the same block and pass the numerator using the AXI4 lite for my HDL model for ZYNQ 706 it does not filters the same signal. why it is behaving differntly in normal simulink simulation and after targetting ZYNQ 706 FPGA. how can i resolve this issue so it can filter the same signal as it is filtering for simulink simulation

Answer 1

[Kiran Kintali]

If your Simulink model has a testbench you can consider generating HDL code with the testbench and verify the generated code in a Simulator. This workflow is automated in HDL Coder using testbench generation capability.

https://www.mathworks.com/help/hdlcoder/ug/test-bench-generation.html

Once you verify the generated HDL code behaves the same as your Simulink model for a given set of inputs you can move to FPGA phase.

For more advanced testbench capabilities such cosimulation of Simulink model and a HDL Simulator in tandem or FPGA in the loop with Simulink you can consider HDL Verifier usage.

https://www.mathworks.com/help/hdlverifier/gs/hdl-cosimulation.html

https://www.mathworks.com/help/hdlverifier/fpga-in-the-loop.html