I have a simulink block which generates the signal at a given frequency. The output of the signal generator is fed into Gain block and later some filters and the output at the last. These blocks are made into subsystems which has signal input and output.
My question is when i convert this simulink block into Xilinx IP using HDL code generator, I get one AXI Lite interface. I have additionlly added AXIS stream as well. so i can control my stream output based one values written to AXI lite from processor. Now i want to change the gain of the sinmulink model inside the subsystem.
Is there any way i can do that? Like i have 100 gain values which needs to be changed and i dont want everytime to go to simulink , change the gain value and generate IP again.
Is it possible to change via AXI lite?or any other mean? Any suggestions is appreciated.
IP core generation example.