Check for root Outports with missing properties

R2026b

mathworks.hism.hisl_0077

Since R2022b

Dependencies: Simulink^® Check™

Usage: High-Integrity System Modeling

Guideline: hisl_0077: Outport interface definition

Description

This check identifies root Outport blocks that are missing property settings.

When you run the check, a results table provides links to Outport blocks and signal objects that do not pass, along with conditions triggering the warning.

Elements under review:

• Simulink

  • Root-level Outport blocks

• System Composer

  • Root-level output ports (architecture models)

Recommended Actions and Results

Review the violations that are flagged by the check and the recommended action for fixing the issue. After applying the changes, save the model and rerun the check analysis.

Modeling Condition	Recommended Action
Model contains Outport blocks that are missing or that inherited port dimensions.	For the listed Outport blocks and signal objects, specify port dimensions.
Model contains Outport blocks that are missing or that inherited data types.	For the listed Outport blocks and signal objects, specify data types.
Model contains Outport blocks that are missing or that inherited sample times.	For the listed Outport blocks and signal objects, specify sample times. The sample times for root outports that have a bus type must match the sample times specified at the leaf elements of the bus object.
Model contains Outport block signal names that implicitly resolve to a Simulink signal object in the base workspace, model workspace, or Simulink data dictionary.	For the listed signal objects, in the property dialog box, select the signal property Signal name must resolve to Simulink signal object. To set this option programmatically, use the port parameter MustResolveToSignalObject.
Output ports of architecture model do not have an assigned data interface.	Assign data interfaces to listed output ports.

Capabilities and Limitations

• Allows exclusions of blocks and charts

• Does not support exclusion in Architecture models

• Does not analyze content of library-linked blocks

• Does not analyze the content in masked subsystems

• Supported by edit-time checking

• Considers the virtuality of the bus object when verifying sample time definitions for a bus element port

  Note

  Implicit resolution to a Simulink signal object is not applicable for signals connected to bus element ports.

• Does not require model compilation

Version History

Introduced in R2022b