PWM

Generate ideal pulse width modulated signal corresponding to input duty cycle

Since R2020b

• 

Libraries:
Simulink / Discontinuities

Description

Use the PWM block to generate an ideal pulse width modulated signal.

Pulse-width modulation (PWM) is a technique for encoding an analog signal using square pulses. This encoding is achieved by controlling the fraction of one period of the square wave that is set to high. This fraction is the duty cycle of the signal. The relationship between the modulated signal and the input duty cycle can be simply described as:

$$\overline{y}=D{y}_{max}+\text{}\left(1-D\right)y_{min}$$

where y_max and y_min are the upper and lower bounds of the output signal, respectively. For the PWM block, the duty cycle is constrained to [0,1]. The ideal PWM signal is proportional to the duty cycle D.

Examples

PWM Control of a Boost Converter

This example shows you how to control a boost converter using the PWM block in Simulink. the boost converter in this model uses the Boost Converter (Simscape Electrical) block from the Simscape™ Electrical™ library.

A PWM signal is used to control the switching device, or gate, of the boost converter. The PID controller generates the command signal, or the duty cycle, to track the desired step-up voltage (Vref) of 18V

This is a relatively high frequency application; the switching gate operates at around 200kHz. Therefore, a pulse period of 1/200,000 or 5e-6s is chosen for the PWM signal.

Given the small time steps, the boostconverter_pwm model provided with the example is loaded from a steady state at 0.069s.

A visualization of the boost converter operation around the 0.1s mark is shown below.

For alternate physical modeling implementations of PWM control, see Pulse Width Modulation (Simscape Electrical).

Ports

Input

D — Duty Cycle

scalar

Desired duty cycle of the pulse P, specified as scalar within the range [0,1].

Data Types: double

Output

Port 1 — Output pulse

scalar

PWM signal corresponding to the input duty cycle.

Data Types: double

Parameters

Period (s) — Pulse width

1 (default) | real scalar

Time between rising edges of consecutive pulses of the output signal. A small value represents a high-frequency pulse.

Programmatic Use

Block Parameter: Period

Type: string | character vector

Values: real scalar

Default: '1'

Initial Delay — Initial delay

0 (default) | real scalar

Specify an initial delay or phase delay for the generated PWM signal, in seconds.

Programmatic Use

Block Parameter: InitialDelay

Type: string | character vector

Values: numeric scalar

Default: 0

Disallow zero duty cycle — Avoid algebraic loops

off | on

Enable this parameter to break algebraic loops containing the PWM block.

Note

Enabling this parameter causes a signal value of 0 or below, which causes the duty cycle input to throw an error.

Programmatic Use

Block Parameter: DisallowZeroDutyCycle

Type: string | character vector

Values: 'on' | 'off'

Default: 'off'

Run at fixed time intervals — Select for discrete time behavior

on (default) | off

Specify when the block executes and the sample time for the output signal.

• off — Block executes each time the delay for an input sample elapses. Output signal has fixed-in-minor sample time.

• on — Block executes at a fixed rate you specify using the Sample time parameter. Output signal has the sample time you specify using the Sample time parameter.

When you select Run at fixed time intervals:

• The delay signal values must be greater than the value you specify for the Sample time parameter.

• Delay signal values that are not integer multiples of the specified sample time are rounded down to the nearest integer multiple of the sample time. For example, if the sample time is 0.1 and the delay signal value is 0.68, the software rounds the delay to 0.6.

Programmatic Use

Block Parameter: RunAtFixedTimeIntervals

Type: string | character vector

Values: 'on' | 'off'

Default: 'off'

Sample Time — Set pulse resolution

0.1 (default) | scalar

Block execution rate and output signal sample time. The delay signal values must be greater than the specified sample time.

When the delay signal value is not an integer multiple of the specified sample time, the software rounds the delay value down to the closest value that is an integer multiple of the sample time. For example, if the sample time is 0.1 and the delay value is 0.68, the software rounds the delay to 0.6.

Dependencies

To enable this parameter, select Run at fixed time intervals.

Programmatic Use

Block Parameter: SampleTime

Type: string | character vector

Values: numeric scalar

Default: 0.1

Block Characteristics

Data Types	double
Direct Feedthrough	no
Multidimensional Signals	no
Variable-Size Signals	no
Zero-Crossing Detection	no

Algorithms

Continuous Sampling Mode

For a pulse starting at time t_k

$$y(t)=\{\begin{array}{cc}1& t_k<t<t_k+pw\\ 0& t_k+pw<t<t_{k+1}\end{array}$$

where pw is the pulse width. For a given period P, pw is proportional to the duty cycle D

$$pw=D(t_k)*P(t_k)$$

Discrete Sampling Mode

In Discrete sampling mode, the input duty cycle signal is sampled at the rate specified by the Run at fixed time intervals parameter.

For a specified sampling rate t_S , the number of samples needed for a pulse of width pw can be expressed as follows

$$\begin{array}{l}{n}_{pw}=\begin{array}{cc}\lfloor \frac{D_k.P_k}{T_S}\rfloor & 0<n_{pw}<n_P\end{array}\\ n_P=\lfloor \frac{P}{T_S}\rfloor \end{array}$$

where n_P is the number of samples needed to simulate a pulse of period P.

Consider a nominal pulse of period P with the sampling rate of the block set to be t_S= 0.25 P. The number of samples needed for one period of the pulse, n_P= 4. Thus, for the input duty cycle D= 0.47 , the number of samples n _pw is floored to $$\lfloor \frac{0.47P}{0.25}\rfloor$$= 1. Therefore, the pulse is high for 1 of the 4 samples in the period.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Not recommended for production-quality code. Relates to resource limits and restrictions on speed and memory often found in embedded systems. The code generated can contain dynamic allocation and freeing of memory, recursion, additional memory overhead, and widely-varying execution times. While the code is functionally valid and generally acceptable in resource-rich environments, smaller embedded targets often cannot support such code.

In general, consider using the Simulink Model Discretizer to map continuous blocks into discrete equivalents that support production code generation. To start the Model Discretizer, in the Simulink^® Editor, on the Apps tab, under Apps, under Control Systems, click Model Discretizer. One exception is the Second-Order Integrator block because, for this block, the Model Discretizer produces an approximate discretization.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

For HDL code generation from this block, the Run at fixed time intervals parameter must be selected.

Version History

Introduced in R2020b