Reference Design Parameters

Parameters available for default reference designs

Since R2023b

Model Configuration Pane: Target

Description

List of the parameters for the reference design. These parameters are the parameters available for the default reference designs that HDL Coder™ supports or the parameters that you define for your custom reference design. For more information, see Define Custom Parameters and Callback Functions for Custom Reference Design.

' ' (Default)

The Reference Design parameter determines the available reference design parameters. Note that the Reference design parameters table requires a string input typed directly into the Value box. These are the main reference design parameters:

• FPGA Data Capture (HDL Verifier required): Generate and integrate the data capture IP into your reference design. Use FPGA data capture to observe signals from your design while the design is running on the FPGA. This parameter captures a window of signal data from the FPGA and returns the data to MATLAB^® or Simulink^® over a JTAG or Ethernet connection. To capture data over a JTAG connection, set this parameter to JTAG. To capture data over an Ethernet connection, set this parameter to Ethernet. Then, map each signal that you want to capture to the FPGA Data Capture interface in the IP Core editor. For more information, see Set Target Reference Design.

  To use this capability, you must install the HDL Verifier™ hardware support packages. See Download FPGA Board Support Package (HDL Verifier).

• Board IP Address: Specify the IP address of the Ethernet port on the target board as a dotted-quad value. The target IP address must be a set of four numbers consisting of integers in the range [0, 255] and separated by three dots. The default value is 192.168.0.2.

  To enable this parameter, set FPGA Data Capture (HDL Verifier required) to Ethernet.

• Insert AXI Manager (HDL Verifier required):

  By default, HDL Coder adds the Insert AXI Manager (HDL Verifier required) parameter to all reference designs. When you set this parameter to JTAG, HDL Coder inserts the JTAG AXI Manager IP into your reference design. When you set this parameter to Ethernet, HDL Coder inserts the UDP AXI Manager IP into your reference design. For more information, see Set Target Reference Design.

  By using the AXI manager IP, you can access the AXI registers in the generated DUT IP core on a hardware board from MATLAB or Simulink through the JTAG or Ethernet connection. See also Set Up AXI Manager (HDL Verifier).

Recommended Settings

No recommendations.

Programmatic Use

Parameter: Reference Design Parameters

Type: N/A

Values: ' '

Default: ' ' (Default)

Version History

Introduced in R2023b