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Force clock

Specify whether the test bench forces clock input signals

Model Configuration Pane: Test Bench

Description

Specify whether the test bench forces clock input signals.

Dependencies

This property enables the Clock high time and Clock high time options. This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Settings

On (default) | Off
On

The test bench forces the clock input signals. When this option is selected, the clock high and low time settings control the clock waveform.

Off

A user-defined external source forces the clock input signals.

Tips

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdltb function.

    makehdltb('sfir_fixed/symmetric_fir', ... 
            'ForceClock', 'off')

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

    hdlset_param('sfir_fixed', 'ForceClock', 'off')
makehdltb('sfir_fixed/symmetric_fir')

Recommended Settings

No recommendations.

Programmatic Use

Parameter: ForceClock
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Version History

Introduced in R2012a