Clock enable delay (in clock cycles)

Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable

Model Configuration Pane: Test Bench

Description

Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable.

Dependencies

This parameter is enabled when Force clock enable is selected.

Settings

1 (default)

The Clock enable delay (in clock cycles) property defines the number of clock cycles elapsed between the time the reset signal is deasserted and the time the clock enable signal is first asserted. In the figure below, the reset signal (active-high) deasserts after 2 clock cycles and the clock enable asserts after a clock enable delay of 1 cycle (the default).

In the figure below, the reset signal (active-high) de-asserts after the interval labelled Hold Time. The clock enable asserts after a further interval labelled Clock enable delay.

Tips

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdltb function.

  makehdltb('sfir_fixed/symmetric_fir', ... 
              'TestBenchClockEnableDelay', 2)

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

  hdlset_param('sfir_fixed', 'TestBenchClockEnableDelay', 2)
  makehdltb('sfir_fixed/symmetric_fir')

Recommended Settings

No recommendations.

Programmatic Use

Parameter: TestBenchClockEnableDelay

Type: integer

Default: 1

Version History

Introduced in R2012a