Downsampler
Libraries:
DSP HDL Toolbox /
Signal Operations
Description
The Downsampler block downsamples an input signal by removing K–1 data samples between input samples. The block supports these combinations of input and output data.
Scalar input and scalar output
Vector input and scalar output
Vector input and vector output
The block provides an architecture suitable for HDL code generation and hardware deployment.
Note
You can also generate HDL code for this hardware-optimized algorithm, without creating a Simulink® model, by using the DSP HDL IP Designer app. The app provides the same interface and configuration options as the Simulink block.
Examples
Ports
Input
data — Input data
scalar | column vector
Input data, specified as a scalar or a column vector with a length up to 64. The input data must be an integer or a fixed point with a word length less than or equal to 128. The Downsample factor (K) parameter must be an integer multiple of the input frame size.
The double
and
single
data types are supported for simulation, but not for HDL
code generation.
Data Types: single
| double
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| fixed point
valid — Valid input data indicator
0
| 1
Control signal that indicates whether the input data is valid. When this value is
1
, the block accepts the values on the data
input port. When this value is 0
, the block ignores the values on
the data input port.
Data Types: Boolean
reset — Option to clear internal states
0
| 1
Control signal that clears the internal states. When this value is
1
, the block stops the current calculation and clears its
internal states. When this value is 0
and
valid is 1
, the block captures data for
processing.
For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.
Dependencies
To enable this port, on the Control Ports tab, select the Enable reset input port parameter.
Data Types: Boolean
Output
data — Downsampled data
scalar | column vector
Downsampled data, returned as a scalar or a column vector with a length up to 1 to 64.
For a vector input, if the vector size is less than or equal to Downsample factor (K), the block outputs scalar output.
Data Types: single
| double
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| fixed point
valid — Valid output data indicator
0
| 1
Control signal that indicates whether data from the data
output port is valid. When this value is 1
, the block returns valid
data on the data output port. When this value is
0
, the values on the data output port are
not valid.
Data Types: Boolean
Parameters
Main
Downsample factor (K) — Downsampling factor
2
(default) | integer in the range [1, 2.^16]
Specify the downsampling factor at which the block decreases the input sample rate.
Sample offset (0 to K-1) — Sample offset
0
(default) | integer in the range [0, 2.^16 – 1]
Specify the sample offset in the range [0, Downsample factor (K) – 1].
Control Ports
Enable reset input port — Option to enable reset input port
off
(default) | on
Select this parameter to enable the reset input port. The reset signal implements a local synchronous reset of the data path registers.
For more reset considerations, see Tips.
Algorithms
Latency
The latency of the block changes according to the length of the input and the sample
offset. V is the length of the input and O is the
sample offset. The latency of block is 1 when you set the Downsample factor
(K) parameter to 1
. This table shows the latency of the
block.
Input Data | Output Data | Latency in Clock Cycles |
---|---|---|
Scalar | Scalar | 2 + O |
Vector | Scalar | 1 + floor (O/V) |
Vector | Vector | 2 |
This figure shows the output of the block with the default configuration, when you set
the Downsample factor (K) and Sample offset (0 to
K-1) parameters to 2
and 0
,
respectively. The latency of the block is two clock cycles and is calculated as 2 +
O, where O is the sample offset.
This figure shows the output of the block when you set the Downsample factor
(K) parameter value to 8
and the Sample offset
(0 to K-1) parameter value to 1
. The latency of the block
is three clock cycles.
This figure shows the output of the block for a two-element column vector input when
you set the Downsample factor (K) and Sample offset (0 to
K-1) parameters to 2
and 0
,
respectively. The latency of the block is one clock cycle.
This figure shows the output of the block for an eight-element column vector input
when you set the Downsample factor (K) parameter value to
4
and the Sample offset (0 to K-1) parameter
value to 1
. The latency of the block is two clock cycles.
Performance
The performance of the synthesized HDL code varies with your target and synthesis options. The performance also varies based on the input data type.
This table shows the resource and performance data synthesis results of the block for a
scalar input and for a 16-element column vector input of type
fixdt(1,16,0)
when you set the Downsample factor
(K) and Sample offset (0 to K-1) parameters to
8
and 0
, respectively. The generated HDL targets the
AMD®
Zynq®- 7000 ZC706 Evaluation Board.
Input Data | Slice LUTs | Slice Registers | Maximum Frequency in MHz |
---|---|---|---|
Scalar | 14 | 37 | 985.58 |
Vector | 18 | 66 | 972.66 |
The resources and frequencies vary based on the type of input data and the value of Downsample factor (K) as well as other parameter values you select in the block mask. Using a vector input can increase the throughput, however, doing so also increases the number of hardware resources that the block uses.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
This block supports C/C++ code generation for Simulink accelerator and rapid accelerator modes and for DPI component generation.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
Version History
Introduced in R2022b
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