owen chang

Last seen: 約4年前 | 2013 年からアクティブ

Followers: 0 Following: 0

連絡

統計

Feeds

質問

why exportONNXNetwork will add additional "Sub" in onnx, how to remove this layer in onnx?
Hi, i did the following: >> baseNetwork = resnet50; >> exportONNXNetwork(baseNetwork,'resnet50-matlab'); but when compare sam...

4年以上前 | 1 件の回答 | 0

1

回答

質問

how to deploy deep learning prototype to FPGA using HDL Coder?
Hi i have FPGA platform and like to play around with Matlab deep learning (like MatConvNet), then deploy on my FPGA platform fo...

6年以上前 | 1 件の回答 | 0

1

回答

質問

running open_system('hdlcoder_led_blinking') for zynq, but no connection?
Hi, i am using usb jtag cable for communication with zynq-zc702, but i can't see serialport as instructed in the webinar, how sh...

10年以上前 | 1 件の回答 | 0

1

回答

質問

how could i generate an axi-stream or axi4-lite dma master by hdl coder?
Hi, i found the current demo using only axi-stream slave interface in sobel image processing system. however, it might require a...

10年以上前 | 1 件の回答 | 0

1

回答

質問

HDL Stream FFT in HDL Coder 2013b, not support AXI4-Stream Interface? (single rate?)
Hi, i have built a system involving Stream FFT with AXI4-Stream Interface, the goal is to put this design into Zynq, so AXI4-St...

10年以上前 | 1 件の回答 | 0

1

回答

質問

Failed Streaming interface is not supported when the DUT is not single rate
Hi, the AXI-Stream interface for Stream FFT is requiring DUT "single rate", but i can't find where to set it, and what does it ...

10年以上前 | 0 件の回答 | 0

0

回答

質問

HDL Stream FFT in HDL Coder 2013b, not support FPGA?
Hi, i am using Stream FFT for Zynq, but once i have created the subsystem and set it to Atomic, i have this error message pop u...

10年以上前 | 1 件の回答 | 0

1

回答

質問

How to create a FFT ipcore for Zynq using Simulink HDL Coder?
there is an error message "not support for frame based module"? is there any other solution for exporting signal processing bl...

10年以上前 | 2 件の回答 | 1

2

回答

質問

Does HDL coder from Simulink support AXI-4 Stream Interface for Xilinx Zynq?
Hi all, I have created an adder example and export to Xilinx Vivado 2013.2 using HDL coder, and integrated using Vivado IPI. th...

10年以上前 | 1 件の回答 | 0

1

回答

owen chang

統計

Thankful Level 1

MATLAB Answers

Feeds

1

1

1

1

1

0

1

2

1