回答済み
warnings in hdl code generation
Begin with one of the predefined HDL templates to avoid such warnings. % Simulink >> create new model >> and select HDL Cod...

約5年前 | 0

回答済み
Convert Code Containing Global Data to Fixed Point
Use Persistent Variables instead of Global Variables when translating MATLAB to HDL Code. See doc and best practices in HDL Code...

約5年前 | 0

回答済み
HDL code generator problem
You need to use streaming inputs for HDL Code Generation. See MATLAB to HDL examples here. >> mlhdlc_demo_setup('heq') >> mlhd...

約5年前 | 0

回答済み
HDL Coder gives Error Message: Evaluation of elaborate function on class hdldefaults.TrigonometricFunction failed
This issue is not reproducible. Attached model uses sin cordic with 11iterations on sfix65 input type. >> makehdl(gcb) ...

約5年前 | 0

回答済み
Simulink HDL Coder D-FF With Trigger that isn't clock
Thanks for attaching reproduction steps. I have used trigger as clock feature to see if this addresses your question. ...

約5年前 | 0

| 採用済み

回答済み
how can i demodulate an FM signal without using any function?
You can refer to product documentation about MATLAB coding style suitable for HDL Code Generation. web(fullfile(docroot, 'hdl...

約5年前 | 0

回答済み
how to connect to enable matlab to be connected to a custom board which not originally from the zynq bendor
Create your own custom reference design for integrating the generated IP core into the target SoC device, Speedgoat board, or ...

約5年前 | 0

回答済み
What is the difference between HDL coder and System Generator blockset?
HDL Coder generates synthesizable RTL code generation from Simulink, MATLAB, Stateflow, and Simscape for ASIC/FPGA soltuions. Xi...

約5年前 | 0

回答済み
I am trying to convert matlab code to verilog HDL (HDL coder), But i am getting the following error, can anyone please suggest a solution.
HDL Code generation from MATLAB requires streaming inputs. Please refer to the following example. >> mlhdlc_demo_setup('heq')

約5年前 | 0

回答済み
Generic port length when integrating existing HDL code with Simulink model using BlackBox
The problem was reproduced and reported to the development team. HDL Coder currently supports value generics (generic values t...

約5年前 | 0

| 採用済み

回答済み
HDL Workflow advisor error
Can you share a small reproduction model and the release you are seeing this issue? Thanks

約5年前 | 0

回答済み
Simulink HDL Coder D-FF With Trigger that isn't clock
Can you share a sample model?

約5年前 | 0

回答済み
HDL Coder streaming input instead of vector
Can you share a sample model that explains your usecase?

約5年前 | 0

回答済み
HDL Workflow advisor on Intel SoC... Error in Quartus while synthesis: Error (272006): In lpm_divide megafunction, LPM_WIDTHN must be less than or equals to 64
Please attach "dut.m" and "testbench.m" file and the HDL Coder project file (.prj) for further analysis and guidance.

約5年前 | 0

回答済み
System Generator: HDL Black Box include mem files.
Are you referring to Xilinx System Generator (XSG) model usecase here? Can you share the model with the issue? What release are ...

約5年前 | 0

回答済み
How to link the fixed point tool result back to HDL coder inside filter design tool?
You can export the filter from FDATool to Simulink via File->Export to Simulink Model, click the “Realize Model” button and run ...

5年以上前 | 0

回答済み
Error when generating test bench
Need dut.m and testbench.m and a project file (with data type settings, HDL settings) to debug such floating point to fixed poit...

5年以上前 | 0

回答済み
HDL Reciprocal speed limitation?
For HDL Code Generation there are now several custom latency choices now available for divide, reciprocal and sqrt fixed-poi...

5年以上前 | 0

回答済み
HDL Coder RAM generation for an array
RAM mapping is an area optimization that maps storage and delay elements in your MATLAB® code to RAM. Without this optimization,...

5年以上前 | 0

回答済み
Error: HDL Verification --> Verify with HDL TestBench
This error is not reproducible in R2020a/R2020b/R2021b versions. Please attach design.m and testbench.m and the project with set...

5年以上前 | 0

回答済み
How to do an HDL Coder design with asynchronous clocks and do resource sharing?
There are many ways to do this in HDL Coder. You can generate code for each clock domain in a seperate DUT IP core or Model Refe...

5年以上前 | 0

回答済み
Error Found unsupported dimensions on matrix type at output port:
Attached are few examples of how to code matrix multiply in HDL Coder.

5年以上前 | 0

回答済み
The fixed-point attributes of the stages of a cascade cannot be changed in FDATOOL. They must be set before cascading
Consider creating a simulink model and generating Verilog HDL from the generated model after further customizations.

5年以上前 | 0

回答済み
Latch logic is detected for variable 'start_token', failed to import Simulink model. Hdl Import parse failed.
I think you have hit a limitation of the Verilog importer. The importer only supports a small subset of Verilog language suitabl...

5年以上前 | 0

回答済み
HDL Coder Buffer Problem
Can you attach the model? Thanks

5年以上前 | 0

回答済み
Getting error while generating hdl code
What version of MATLAB and HDL Coder are you currently using? Can you share output of 'ver' command? I wonder if you have an b...

5年以上前 | 1

回答済み
Implementation of a SystemVerilog block in a Simulink simulation
https://www.mathworks.com/help/hdlverifier/matlab-cosimulation.html Consider using cosimulation feature. You can also integr...

5年以上前 | 0

回答済み
Can SimEvent library components be used with HDL Coder?
HDL Code Generation is supported for SimEvents Blocks. Consider sharing your usecases by reaching out to support@mathworks.com...

5年以上前 | 0

回答済み
Trenz Electronic TE0820 support in HDL coder toolbox
>> I want to create the algorithm as Simulink models and execute these models in Simulink external mode for debuging and data ga...

5年以上前 | 0

| 採用済み

回答済み
HDL Code Generation Block Support
HDL Coder specific library in Simulink provides few HDL friendly blocks like RAM, FIFO etc., that are suited for HDL code genera...

5年以上前 | 0