Implementation of a SystemVerilog block in a Simulink simulation
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Hello all,
I have a synthesizable SV module that has been tested on an FPGA and as a part of a fabricated IC.
I would like to use this block in a Simulink simulation.
Would appriciate any help\thoughts since I could not find any relevant material online.
Thanks,
Tom
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回答 (1 件)
Kiran Kintali
2021 年 3 月 13 日
Consider using cosimulation feature.
You can also integrate customer HDL Code in MATLAB using blackbox features in HDL Coder
https://www.mathworks.com/help/hdlcoder/ref/hdl.blackbox-system-object.html
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