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Referenced model output of three phase voltage and current are 65535
I had converted the matlab function block into referenced model for running in Processor-In-Loop (PIL) and I had kept the code i...
28日 前 | 1 件の回答 | 0
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Autogenerated VHDL for FPGA - In - The Loop DUT I/O Issue "** HDL Parser Error: line XX: near "vector_of_std_logic_vector32", found unsupported data-type "vector_of_std_logic_vector32""
In HDL coder setting enable Scalarize ports. Steps for enabling Scalarize ports: HDL code --> Setting --> Configuration parame...
Autogenerated VHDL for FPGA - In - The Loop DUT I/O Issue "** HDL Parser Error: line XX: near "vector_of_std_logic_vector32", found unsupported data-type "vector_of_std_logic_vector32""
In HDL coder setting enable Scalarize ports. Steps for enabling Scalarize ports: HDL code --> Setting --> Configuration parame...
約2ヶ月 前 | 0
質問
sampling time mismatch in simulink and harware
i am having a simulink model in matlab which is running on sampling time of 5e-6 second now i want to run my matlab file in zedb...
約2ヶ月 前 | 2 件の回答 | 0
