Julien

Last seen: 4ヶ月前 | 2024 年からアクティブ

Followers: 0 Following: 0

統計

バッジを表示

Feeds

質問

Can you use switches as inputs in a design tested with FPGA-in-the-Loop simulation? (on a Zedboard)
Hello, I am currently testing the abilities of the HDL Verifier Toolbox. I tried the FIL simulation with a design and it works....

4ヶ月前 | 1 件の回答 | 0

1

回答

質問

HDL Verifier "Verify HDL Module with MATLAB Test Bench" Tutorial: Cannot find example code from Tutorial.
Hello, I tried to do the "Verify HDL Module with MATLAB Test Bench" Tutorial for the HDL Verifier add-on. In the "Set up Tutoria...

5ヶ月前 | 1 件の回答 | 0

1

回答