photo

Devendra Bhave

MathWorks

Last seen: 7日 前 |  2020 年からアクティブ

Followers: 0   Following: 0

I am a Senior Software Engineer at MathWorks. My major responsibilities are Simulink Design Verifier and verification and validation workflows.
DISCLAIMER: Any advice or opinions here are my own, and in no way reflect that of MathWorks.

統計

All
  • Personal Best Downloads Level 1
  • First Submission
  • Knowledgeable Level 1
  • First Answer
  • Revival Level 1

バッジを表示

Feeds

表示方法

回答済み
Set design verifiers parameters programmatically
Use parameter DVMaxProcessTime to set maximum analysis time. You must save the model before calling sltest.testmanager.createTe...

3年弱 前 | 0

回答済み
Facing issue in test generation using simulink test through matlab commands
It is a bit difficult to establish the root cause of the error based on the above information. I suggest you consult MathWorks t...

3年弱 前 | 0

回答済み
Loading results from an excel sheet and launching Simulink Design Verifier again to produce a new Simulink Design Verifier Report
Hi Marco, SLDV supports extending existing test cases to achieve 100% coverage. Let's call the set of test cases you authored ...

4年弱 前 | 0

| 採用済み

回答済み
Loading results from an excel sheet and launching Simulink Design Verifier again to produce a new Simulink Design Verifier Report
Hi Marco, I understand your query as follows: You are running SLDV test generation analysis on your model to get 100% coverage...

4年弱 前 | 0

回答済み
Can a different initial Stateflow state be set for a test case/harness?
As per my understanding, you are expecting the default transition of Stateflow Chart to enter in your specified state. Adding...

4年弱 前 | 0

回答済み
Central bus initialization in testsequence for multiple harnesses
As per my understanding, you are expecting to call custom code before simulating the harness in Simulink Test Manager. Simulink...

4年弱 前 | 0