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Kranti Balaga

Last seen: 約2ヶ月 前 2021 年からアクティブ

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Is it possible to extend the bus width from 32bit(16 for I,16 for Q) to 64bit(32 for I, 32 for Q) in HDL QAM Transmitter and Receiver?
We dont have an option to do automatically by configuring a parameter. You can start changing the symbol modulator and pulse sha...

2ヶ月 前 | 0

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HDL QPSK Transmitter and Receiver CFO problem
Yes, simply you can provide the Symbol rate in the Inputdata mask, change the Carrier Frequency Offset (in Hz) corresponding to...

5ヶ月 前 | 0

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HDL QPSK Transmitter and Receiver CFO problem
Hi Ali Shan, I am fine, hope you are doing well. The more average length gives a better/accurate estimate, but that d...

5ヶ月 前 | 0

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HDL QPSK Transmitter and Receiver CFO problem
Hi Ali Shan, The value 0.125 implied in the algorithm that we choose. Implemented correlation based estimation, as the r...

5ヶ月 前 | 0

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HDL QPSK Transmitter and Receiver CFO problem
Hi Ali Shan, In QPSK single carrier model, the carrier frequency estimates in steps of coarse and fine estimates which a...

5ヶ月 前 | 0

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Modifying the QPSK RX for TDD for hw/sw design in ad9361
Hi Muhammad, The Model you are referring is not supported for discrete valid of inputs, and the receiver is expecting alw...

約1年 前 | 0

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HDL optimized QPSK TX and RX combined
Hi, There are some limitations in the model due to receiver architecture. Here, Timing recovery would be self synchronizin...

1年以上 前 | 0

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Addition of signals in simulink
Hi, To demodulate the I and Q signals without using QPSK demodulator block can be done for the hard decision. You can get I...

1年以上 前 | 0