HDL Coder Evaluation Reference Guide
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HDL-Coder-Evaluation-Reference-Guide
Guidelines for getting started using HDL Coder to generate VHDL or Verilog to target FPGA or ASIC hardware. The document provides practical guidance for:
- Setting up your MATLAB algorithm or Simulink model for HDL code generation
- How to create HDL-ready Simulink models, Stateflow charts, and MATLAB Function blocks
- Tips and advanced techniques for HDL code generation
- Code generation settings for specific FPGA/SoC targets, including AXI interfaces
- Converting to fixed-point or utilizing native floating-point
- Optimizing for various goals and targets
- Verifying your generated code
Examples are included to illustrate selected concepts.
引用
MathWorks HDL Coder Team (2024). HDL Coder Evaluation Reference Guide (https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v4.0.0), GitHub. 取得済み .
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- Code Generation > HDL Coder >
- FPGA, ASIC, and SoC Development > HDL Coder >
- Code Generation > HDL Verifier >
- FPGA, ASIC, and SoC Development > HDL Verifier >
- FPGA, ASIC, and SoC Development >
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Examples
バージョン | 公開済み | リリース ノート | |
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4.0.0 | See release notes for this release on GitHub: https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v4.0.0 |
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3.0.0 | See release notes for this release on GitHub: https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/releases/tag/v3.0.0 |
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2.4.0.0 | Updated for R2018b |
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2.3.0.0 | Japanese translation of R2017b update |
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2.2.0.0 | Updated to R2017b |
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2.1.0.0 | Updated Japanese version for R2016b |
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2.0.0.0 | Updated for R2016b |
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1.1.0.0 | Added Japanese version of the guide |
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1.0.0.0 |