Reading Data from PMOD ADC through I2C

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Jay C
Jay C 2020 年 11 月 16 日
コメント済み: Cau Tran 2022 年 8 月 22 日
I am trying to read data PMOD ADC (Digilent AD2) which uses I2C using HDL Coder for a Zynq-7000 FPGA (ZedBoard).
I found a documentation on the I2C Core Generation for Audio Codec Chip from the following link: https://www.mathworks.com/help/hdlcoder/ug/ip-core-generation-of-an-i2c-controller-ip-to-configure-the-audio-codec-chip.html
This document states that "I2C Master Controller only support I2C write and doesn't support I2C readback". Does this mean that I can't use this IP for interfacing with all devices that communicate data with FPGA through I2C (e.g. sensor, ADC)? Or does "I2C readback" mean something different from "reading data through I2C"? I am wondeirng if anyone knows if there is an I2C controller example that I could use to read data through I2C interface from ADC.
Thanks!
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Walter Roberson
Walter Roberson 2020 年 11 月 16 日
編集済み: Walter Roberson 2020 年 11 月 17 日
https://www.mathworks.com/help/soc/ref/i2cmaster.html shows a sequence for reading data from a slave with xilinx
Jay C
Jay C 2020 年 11 月 16 日
Thank you. I will check it out!!

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回答 (1 件)

Wang Chen
Wang Chen 2021 年 6 月 30 日
Hi Jay,
Yes, I2C readback need some extra logic. The HDL Coder example model you mentioned only do I2C write.
As Walter mentioned, the SoC Blockset I2C Master block can support both read and write on I2C bus.
https://www.mathworks.com/help/soc/ref/i2cmaster.html
Thanks,
Wang
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Cau Tran
Cau Tran 2022 年 8 月 22 日
Hi Wang,
I am using I2CMaster clock, but I have some confuse for something:
  • The block has SDA, SCL, SDAIn, SCLIn, but It confilcts with I2C protocol.
  • I am trying to simulate this block but it not run well.
Please explain detail for firt question?
Do you have example for this block? Please send me.
Thanks you so much.

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