How do you generate a registered output from Stateflow?
1 回表示 (過去 30 日間)
古いコメントを表示
If I have an output from a Stateflow diagram; in the generated HDL code the output is assigned from the next state decision logic (combinatorial) _next signal and not from the clocked process, _reg signal. As best practice is to have all outputs from a module being registered a unit delay is added to the output external to the stateflow. However when the generated code is synthesised this register is identified as an equivalent register to the equivalent _reg signal and removed, generating a warning.
How do I generate an output from stateflow that is sourced from the _reg signal as opposed to the the _next signal so that I do not need to put unit delays external to the stateflow diagram?
0 件のコメント
回答 (2 件)
Michael Felger
2023 年 5 月 26 日
Update: starting with R2022b, the ClockDrivenOutput parameter for stateflow is available for Moore charts.
With this, registered output is generated.
0 件のコメント
参考
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!