"Data-type 'Fix_16_13' is unsupported for HDL code generation "
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I am trying to translate my Simulink design to Verilog code from HDL work flow advisor but i get the following error "Data-type 'Fix_16_13' is unsupported for HDL code generation " can you please help me out in this. I am using CORDIC SINCOS core to generate sine wave its output is of Fix_16_13 and workflow advisor is giving error on this output.
回答 (1 件)
Tim McBrayer
2012 年 6 月 13 日
You need to find where you have specified "Fix_16_13" and correct the syntax. The string "Fix_16_13" is not a valid Simulink data type specification. If this string is intended to be a Simulink data type string, it should be fixdt(0,16,13) if unsigned, and fixdt(1,16,13) if the type is a signed type.
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