I would like to complete this workflow example:
https://www.mathworks.com/help/hdlcoder/examples/define-and-register-custom-board-and-reference-design-for-soc-workflow.htmlefine and Register Custom Board and Reference Design for SoC Workflow
Like in the tutorial, I made a custom reference block design, without any AXI peripheral, because hdl coder will provide that. But at this point I am not able to validate my design in vivado, with axi_interconnect_0/M00_AXI port unconnected.
Later, when the hdl workflow advisor tries to "create project" (at workflow stage 4.1), the generated "vivado_create_prj.tcl" runs "validate design", and fails. (workspace/hdl_prj/vivado_ip_prj/vivado_create_prj.tcl)
Is there any way to workaround this issue?