- Put your comparision logic in subsystem.
- Put an Enable port in the same subsystem.Make sure that State when enabling property of your enable block is set to held.
- Connect output of an Unit delay block to enable port of this subsystem.For unit delay block set Sample time-->-1, Initial condition-->1
- Connect a constant block to the input of Unit delay.For constant block set Constant Value-->0
how to compare for just one time in simulink
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in my circuit in simulink i have to compare the current with a constant and if this current is above some value it would disconnect one resistor but when this happens the current will be under the value spicified and the resistor is connected and it stays between connecting and disconnecting all the time of simulation . i wonder how to compare for just one time and keep the same value of the output signal from the compare to constant block after the comparision
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2012 年 5 月 15 日
Put your comparision logic in enabled subsystem and enable the subsystem only on first sample time.
There can be many ways of enabling subsystem for only first sample time. One of which is as below
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Keerthi Shankar
2022 年 3 月 4 日
Do u know how to do that to compare values of signals from time to time...,?
Garvit Amipara
2022 年 4 月 4 日
@@Adrián Tham Ochoa I have been using variable time delay block for that purpose with external input for delay time and set it to constant, in your case 2 sec. In my case, the issue with this block is that it slows the whole simulation, consumes buffer size (used to save the data during the delayed time for continous delayed output).
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