conversion of subsystem to reference model, and merge block port sizing

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Randy
Randy 2017 年 9 月 29 日
コメント済み: Randy 2017 年 12 月 6 日
I have a subsystem I would like to convert to a reference model. The subsystem compiles in external mode without problems within a larger system. When I attempt to convert this subsystem to a reference model, the Conversion Advisor starts complaining about unequal port widths through merge blocks despite the fact that these merge blocks have the "Allow unequal port widths" box checked.
How do I fix this? My system requires variable width data.
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Nick Choi
Nick Choi 2017 年 10 月 2 日
Could you provide a minimized reproduction model? It would be helpful to see what is happening within the model.
Randy
Randy 2017 年 12 月 6 日
I believe the root problem is that while merge blocks do support unequal widths, they don't support variable size signals passing through them.

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