getting error while converting matlab code to verilog

while converting matlab to verilog in hdl coder error getting testbench. ERROR : Error using eml_error (line 20) BIT must be integers between 1 and 9 for embedded.fi. i cannot even understand meaning of that error, can u figure it out

Answer 1

[Bharath Venkataraman]

Do you have any bit manipulation code? In that case, one guess is that the index you are passing needs to be between 1 and 9, where as the value you are passing in is not between those values. Showing the code here may help debug it.