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How to access AXI-registers of IP-blocks that are already part of custom reference design, not generated with HDLCoder?

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Jarno Tuominen
Jarno Tuominen 2017 年 4 月 8 日
回答済み: Wang Chen 2021 年 6 月 30 日
Hi,
Some challenges with Zedbard/Zynq-7000 HW-/SW-codesign. Accessing the AXI-mapped registers of an IP-block generated from Simulink with HDLCoder is trivial - but what if I have created a custom reference design, which includes IP-blocks with AXI-interface?
In my trial case, I took a Xilinx AXI-I2C-core, put that into a custom reference design and created an extra, empty AXI-stub for additional AXI-device. From Simulink I'm generating another IP-block (the counter/ledblinker demo), which fits in nicely in to the free slot in AXI interconnect. Leds are blinking and the real-time control from Simulink works, Cortex A9 running Linux, just like in the examples. So, the HW/HDL flow works nicely. Next, I would like to start using the I2C interface in a similar way - writing and reading to it from Simulink real-time, using the generated interface model as a starting point.
I do have some ideas where to start, but at this point I would like to hear if anybody else have tried to do similar thing. Also, if there's an easy way to get Zynq-7000's ARM I2C-peripheral block working with this kind of hardware-in-the-loop set-up, I would be interested to hear :)
Jarno
  1 件のコメント
Anirudh  Acharya
Anirudh Acharya 2017 年 11 月 5 日
Hi Jarno,
I am facing the same problem. Did you find any solution or documentation addressing this problem?
Best Regards, Anirudh

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回答 (1 件)

Wang Chen
Wang Chen 2021 年 6 月 30 日
Hi Jiarno,
HDL Verifier has a MATLAB as AXI Master feature, which you can from MATLAB to control different IPs in your FPGA design, via the JTAG interface.
You can connect the non-HDL Coder generated IP to the JTAG Master as AXI Master IP in your custom reference design. Then from MATLAB, you can read/write these registers from MATLAB. Please refer to following example:
https://www.mathworks.com/help/hdlcoder/ug/using-jtag-as-axi-master-to-control-hdl-ip-core.html
You can also access the IPs in your FPGA design through Ethernet interface if you are using a SoC device, trhough the MATLAB FPGA prototyping API. Please refer to following example:
Thanks,
Wang

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