Is it possible to test a HDL design with multiple clocks using FPGA-in-the loop and Simulink?

I would like to test a design using FPGA-in-the-loop simulation. ¿Is it possible to test a design that contains multiple clocks with different frequencies? (200MHz,100MHz,50 MHz and 25 MHz).

Thanks

Answer 1

[Tao Jia]

FPGA-in-the-Loop does not support multiple asynchronous clocks. If all your clocks are synchronous, i.e., they are derived from the same clock, it might work, but you'll probably have perform some manual modification to the FPGA-in-the-Loop generated FPGA project to make that work.