filter design and sampling rate

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Daniel
Daniel 2016 年 5 月 26 日
Hi, i am using the fdtool to design an HPF.
i have an ADC that goes to a FPGA. the FPGA clock i will be using is 20MHz i want to filter 10kHZ signal and want to pass from 300Khz I have 256 multipliers.
using the FDATOOL i get a very large FILTER order should i lower the FPGA clock , use the FILTER and then speed up the clock again?

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