HDL IFFT optimize latency

Hi; I used Optimize HDL IFFT but i have latency delay in the output which a lot of zero i think it is the like a time delay of real time processing. My question is how can i remove this zero in the output

Answer 1

[Bharath Venkataraman]

The latency indicates the real-life behavior of the system on an FPGA or ASIC. To look at the data only when it is valid, use the valid output of the block and look at the data only when the validOut is high.

[sameer al-obaidi]

thank you; the B.W is reduced due to the delay and i want to transmit the data without delay can i do that or not and how?

[Bharath Venkataraman]

In the actual system, you cannot run faster than one sample/clock, so if you do want to reduce your latency, you will need to precompute the output, store it and send it faster.

[sameer al-obaidi]

How can implement pre-compute data. I try to store in workspace and import after that but HDL coder not support import data. please, can I implemented by other methods.

[Bharath Venkataraman]

For your purposes, I believe you should take the output of the IFFT, and send it to a To Workspace block along with the validOut. In MATLAB, you can look at the data for all the indices which have validOut high. If the To Workspace output variables are dataOut and validOut, dataOut(validOut) -> should give you all the data when validOut is high.