failed to receive a control packet from the FPGA target
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Hi,
I am trying to perform the simulink example (fil_pid) using MATLAB 2014b, Vivado 2014.1, and Xilinx VC707 board. I performed all the steps successfully as shown in the figures below.
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However, when I replace the controller and try to simulate the design, it gives me this error message:

I tried to check the connection with the FPGA (using ping command), and I found that it is working well. And the FPGA programming file is downloaded successfully.
So, I do not know what is really the problem.
Thanks.
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Jazmin
2019 年 9 月 13 日
Hello, did you solve the problem, I found the same mistake, I'musing Atlys Spartan 6 development board... Please, need help
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